1. Field of the Invention
This present invention relates to a structure of nonvolatile memory, and more particularly to a structure of nonvolatile memory with low source line sheet resistance.
2. Description of the Prior Art
Nonvolatile memory array is a well-known and useful structure in an integrated circuit. It is always one of the study objects to improve the reliability and the operating performance of a nonvolatile memory array.
FIG. 1A is a top view of a structure of a nonvolatile memory array in the prior art. Referred to FIG. 1A, the nonvolatile memory array comprises a plurality of shallow trench isolation 110, a plurality of second polysilicon layer 120, and a plurality of contact 130. The second polysilicon layer 120 may be the word line of the above-mentioned nonvolatile memory array. The above-mentioned nonvolatile memory array further comprises a source line. The source line is disposed in the A–A′ direction in FIG. 1A.
FIG. 1B is a cross-section (A–A′) view of FIG. 1A. According to FIG. 1B, a plurality of shallow trench isolation 110 is disposed in the substrate 100. A source line 140 is formed on the surface of the substrate 100 and under the shallow trench isolation 110. From FIG. 1B, it can be found that portions of the source line 140 are recessed by the shallow trench isolation 110, and thus the topology of the high-step (the source line on the surface of the substrate) and the low-step (the source line under the shallow trench isolation) profile is formed in the source line 140. The source line sheet resistance will be raised by the recess of the source line.
FIG. 1C is a cross-section (B–B′) view of FIG. 1A. As shown in FIG. 1C, besides the shallow trench isolation 110 and the source line 140, the nonvolatile memory array further comprises a plurality of drain regions 150 in the substrate 100. The nonvolatile memory array further comprises a plurality of first polysilicon layer 160 on the substrate 100, and a plurality of second polysilicon layer 120 on the first polysilicon layers, respectively. The first polysilicon layer 160 and the second polysilicon layer 120 can construct the gate structure of the above-mentioned nonvolatile memory array.
FIG. 1D is a cross-section (C–C′) view of FIG. 1A. As shown in FIG. 1D, because of the shallow trench isolation 110 disposed in the source line 140, the recess of the source line 140 is occurred. While the above-mentioned nonvolatile memory array is operated, the recess of the source line 140 will raise the source line sheet resistance, and thus the reliability and the operating performance of the nonvolatile memory array will be decreased.
Hence, it is an important object of developing a structure of nonvolatile memory array with low source line sheet resistance. Moreover, the above-mentioned nonvolatile memory array can increase the reliability and the operating performance of the nonvolatile memory array.